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ultralow distortion, ultralow noise op amp ad797 rev. h information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one t u.s.a. tel: 781. .com fax: 781.461.3113 ?2002-2010 analog devices, inc. all rights reserved. echnology way, p.o. box 9106, norwood, ma 02062-9106, 329.4700 www.analog features low noise 0.9 nv/hz typical (1.2 nv/hz maximum) input voltage noise at 1 khz 50 nv p-p input voltage noise, 0.1 hz to 10 hz low distortion ?120 db total harmonic distortion at 20 khz excellent ac characteristics 800 ns settling time to 16 bits (10 v step) 110 mhz gain bandwidth (g = 1000) 8 mhz bandwidth (g = 10) 280 khz full power bandwidth at 20 v p-p 20 v/s slew rate excellent dc precision 80 v maximum input offset voltage 1.0 v/c v os drift specified for 5 v and 15 v power supplies high output drive current of 50 ma applications professional audio preamplifiers ir, ccd, and sonar imaging systems spectrum analyzers ultrasound preamplifiers seismic detectors - adc/dac buffers general description the ad797 is a very low noise, low distortion operational amplifier ideal for use as a preamplifier. the low noise of 0.9 nv/hz and low total harmonic distortion of ?120 db in audio bandwidths give the ad797 the wide dynamic range necessary for preamps in microphones and mixing consoles. furthermore, the ad797 has an excellent slew rate of 20 v/s and a 110 mhz gain bandwidth, which makes it highly suitable for low frequency ultrasound applications. the ad797 is also useful in infrared (ir) and sonar imaging applications, where the widest dynamic range is necessary. the low distortion and 16-bit settling time of the ad797 make it ideal for buffering the inputs to - adcs or the outputs of high resolution dacs, especially when the device is used in critical applications such as seismic detection or in spectrum analyzers. key features such as a 50 ma output current drive and the specified power supply voltage range of 5 v to 15 v make the ad797 an excellent general-purpose amplifier. 00846-002 5 0 10m 3 1 100 2 10 4 1m 100k 10k 1k frequency (hz) input voltage noise (nv/ hz) figure 1. ad797 voltage noise spectral density table 1. low noise op amps voltage noise 0.9 nv 1.1 nv 1.8 nv 2.8 nv 3.2 nv 3.8 nv single ad797 ad8597 ada4004-1 ad8675 / ada4075-2 op27 ad8671 dual ad8599 ada4004-2 ad8676 op270 ad8672 quad ada4004-4 op470 ad8674
ad797 rev. h | page 2 of 20 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 absolute maximum ratings ............................................................ 5 pin configuration ............................................................................. 5 thermal resistance ...................................................................... 5 esd caution .................................................................................. 5 typical performance characteristics ............................................. 6 theory of operation ...................................................................... 11 noise and source impedance considerations ........................... 12 low frequency noise ................................................................ 12 wideband noise ......................................................................... 12 bypassing considerations ......................................................... 13 the noninverting configuration ............................................. 13 the inverting configuration .................................................... 14 driving capacitive loads .......................................................... 14 settling time ............................................................................... 14 distortion reduction ................................................................. 15 outline dimensions ....................................................................... 18 ordering guide .......................................................................... 19 revision history 6/10rev. g to rev. h added table 1; renumbered sequentially .................................... 1 moved figure 1 to absolute maximum ratings section; renumbered sequentially ................................................................ 5 changes to table 3 ............................................................................ 5 added thermal resistance section and table 4 .......................... 5 moved figure 3 to typical performance characteristics section .............................................................................................. 10 change to noise and source impedance considerations section .............................................................................................. 12 changes to ordering guide .......................................................... 19 9/08rev. f to rev. g changes to input common-mode voltage range parameter, table 1 ................................................................................................ 3 1/08rev. e to rev. f changes to absolute maximum ratings ....................................... 5 change to equation 1 ..................................................................... 12 changes to the noninverting configuration section ................ 13 updated outline dimensions ....................................................... 19 changes to ordering guide .......................................................... 20 7/05rev. d to rev. e updated figure 1 caption ................................................................ 1 deleted metallization photo ............................................................ 6 changes to equation 1 ................................................................... 12 updated outline dimensions ....................................................... 19 changes to ordering guide .......................................................... 20 10/02rev. c to rev. d deleted 8-lead cerdip package (q-8) ......................... universal edits to specifications ....................................................................... 2 edits to absolute maximum ratings .............................................. 3 edits to ordering guide ................................................................... 3 edits to table i ................................................................................... 9 deleted operational amplifiers graphic .................................... 15 updated outline dimensions ....................................................... 15
ad797 rev. h | page 3 of 20 specifications t a = 25c and v s = 15 v dc, unless otherwise noted. table 2. ad797a ad797b parameter conditions supply voltage (v) min typ max min typ max unit input offset voltage 5 v, 15 v 25 80 10 40 v t min to t max 50 125/180 30 60 v offset voltage drift 5 v, 15 v 0.2 1.0 0.2 0.6 v/c input bias current 5 v, 15 v 0.25 1.5 0.25 0.9 a t min to t max 0.5 3.0 0.25 2.0 a input offset current 5 v, 15 v 100 400 80 200 na t min to t max 120 600/700 120 300 na open-loop gain v out = 10 v 15 v 1 20 2 20 v/v r load = 2 k 1 6 2 10 v/v t min to t max 1 15 2 15 v/v r load = 600 1 5 2 7 v/v t min to t max 14,000 20,000 14,000 20,000 v/v @ 20 khz 1 dynamic performance gain bandwidth product g = 1000 15 v 110 110 mhz g = 1000 2 15 v 450 450 mhz C3 db bandwidth g = 10 15 v 8 8 mhz full power bandwidth 1 v out = 20 v p-p, r load = 1 k 15 v 280 280 khz slew rate r load = 1 k 15 v 12.5 20 12.5 20 v/s settling time to 0.0015% 10 v step 15 v 800 1200 800 1200 ns common-mode rejection v cm = cmvr 5 v, 15 v 114 130 120 130 db t min to t max 110 120 114 120 db power supply rejection v s = 5 v to 18 v 114 130 120 114 db t min to t max 110 120 130 120 db input voltage noise f = 0.1 hz to 10 hz 15 v 50 50 nv p-p f = 10 hz 15 v 1.7 1.7 2.5 nv/hz f = 1 khz 15 v 0.9 1.2 0.9 1.2 nv/hz f = 10 hz to 1 mhz 15 v 1.0 1.3 1.0 1.2 v rms input current noise f = 1 khz 15 v 2.0 2.0 pa/hz input common-mode voltage range 15 v 11 12 11 12 v 5 v 2.5 3 2.5 3 v output voltage swing r load = 2 k 15 v 12 13 12 13 v r load = 600 15 v 11 13 11 13 v r load = 600 5 v 2.5 3 2.5 3 v short-circuit current 5 v, 15 v 80 80 ma output current 3 5 v, 15 v 30 50 30 50 ma
ad797 rev. h | page 4 of 20 ad797a ad797b parameter conditions supply voltage (v) min typ max min typ max unit total harmonic distortion r load = 1 k, c n = 50 pf, f = 250 khz, 3 v rms 15 v ?98 ?90 ?98 ?90 db r load = 1 k, f = 20 khz, 3 v rms 15 v ?120 ?110 ?120 ?110 db input characteristics input resistance differential 7.5 7.5 k common mode 100 100 m input capacitance differential 4 20 20 pf common mode 5 5 pf output resistance a v = 1, f = 1 khz 3 3 m power supply operating range 5 18 5 18 v quiescent current 5 v, 15 v 8.2 10.5 8.2 10.5 ma 1 full power bandwidth = slew rate/2 v peak . 2 specified using external decompensation capacitor. 3 output current for |v s ? v out | > 4 v, a ol > 200 k. 4 differential input capacitance consists of 1.5 pf package capacitance and 18.5 pf from the input differential pair.
ad797 rev. h | page 5 of 20 absolute maximum ratings table 3. parameter ratings supply voltage 18 v input voltage v s differential input voltage 1 0.7 v output short-circuit duration indefinite within maximum internal power dissipation storage temperature range (n, r suffix) ?65c to +125c operating temperature range ?40c to +85c lead temperature (soldering 60 sec) 300c 1 the ad797 inputs are protected by ba ck-to-back diodes. to achieve low noise, internal current-limiting resistors are not incorporated into the design of this amplifier. if the differential input voltage exceeds 0.7 v, the input current should be limited to less than 25 ma by series prot ection resistors. note, however, that this degrades the low noise performance of the device. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. pin configuration decompens a tion and distortion neutralization +v s output offset null 8 ad797 top view o ffset null 1 ?in 2 +in 3 ?v s 4 7 6 5 00846-001 figure 2. 8-lead plastic dual in-line package [pdip] and 8-lead standard small outline package [soic] thermal resistance ja is specified for the device soldered on a 4-layer jedec standard printed circuit board (pcb) with zero airflow for the soic package, and a 2-layer jedec standard printed circuit board (pcb) with zero airflow for the pdip package. table 4. thermal resistance package type ja jc unit 8-lead soic (r-8) 120 43 c/w 8-lead pdip (n-8) 103 50 c/w esd caution
ad797 rev. h | page 6 of 20 typical performance characteristics 00846-004 0 20 5 10 15 supply voltage (v) 20 0 15 5 10 input common-mode range (v) figure 3. input common-mode vo ltage range vs. supply voltage 00846-00 0 20 5 10 5 output voltage swing (v) 20 0 15 5 10 15 supply voltage (v) ?v out +v out figure 4. output voltage swing vs. supply voltage 00846-00 load resistance ( ? ) 0 10 100 10k 1k 6 output voltage swing (v p-p) 30 10 20 v s = 5 v s = 15v figure 5. output voltage swing vs. load resistance 00846-007 horizontal scale (5sec/div) vertic a l scale (0.01v/div) figure 6. 0.1 hz to 10 hz noise 00846-008 temperature (c) input bias current (a) ?60 140 ?40 100 120 80604020 0 ?20 ?2.0 ?1.5 ?1.0 ?0.5 0 figure 7. input bias current vs. temperature 00846-009 temperature (c) short-circuit current (ma) 140 140 100 60 ?40 80 ?60 120 120100 80 604020 0 ?20 40 source current sink current figure 8. short-circuit current vs. temperature
ad797 rev. h | page 7 of 20 00846-010 supply voltage (v) 20 51 5 0 10 6 quiescent supply current (ma) 11 9 7 8 10 +125c +25c ?55c figure 9. quiescent supply current vs. supply voltage 00846-011 supply voltage (v) output voltage (v rms) 1 2 9 3 6 0 0 20 5 10 15 f = 1khz r l = 600 ? g = +10 figure 10. output voltage vs. supply voltage for 0.01% distortion 00846-012 step size (v) settling time (s) 1.0 0.6 0.2 0.4 0.8 0 10 2 0 8 6 4 0.0015% 0.01% figure 11. settling time vs. step size () 00846-013 frequency (hz) power supply rejection (db) 20 1m 80 40 10 60 1 120 100 100k 10k 1k 100 140 50 75 100 125 150 175 200 cmr common mode rejection (db) psr ?supply psr +supply figure 12. power supply and common-mode rejection vs. frequency 00846-014 output level (v) thd + noise (db) ? 60 ?100 ?120 0.01 0.1 10 1 ?80 r l = 600 ? g = +10 f = 10khz noise bw = 100khz v s = 5v v s = 1 5v figure 13. total harmonic distortion (thd) + noise vs. output level 00846-015 30 10 0 10k 100k 10m 1m 20 5v supplies 15v supplies r l = 600 ? frequency (hz) output voltage (v p-p) figure 14. large-signal frequency response
ad797 rev. h | page 8 of 20 00846-016 5 3 1 2 4 input voltage noise (nv/ hz) 0 10m 100 10 1m 100k 10k 1k frequency (hz) figure 15. input voltage noise spectral density 00846-017 frequency (hz) 0 100m 1k 100 10m 1m 100k 10k open-loop gain (db) 120 60 20 40 100 80 100 80 60 40 20 0 phase margin (degrees) phase margin gain without r s * without r s * with r s * with r s * *r s = 100 *see figure 25. figure 16. open-loop gain and phase margin vs. frequency 00846-018 temperature (c) ?60 140 ?40 100 120 80604020 0 ?20 input offset current (na) 300 150 0 ?150 ?300 under compensated overcompensated figure 17. input offset current vs. temperature 00846-019 temperature (c) slew r a te (v/s) gain/bandwidth product (mhz (g = 1000)) ?60 140 ?40 100 120 80 60 4020 0 ?20 120 110 100 90 80 35 30 25 20 15 gain/bandwidth product slew rate rising edge slew rate falling edge figure 18. slew rate and gain/bandwidth product vs. temperature 00846-020 load resistance ( ? ) open-loop gain (db) 100 10k 1k 160 100 120 140 figure 19. open-loop gain vs. load resistance 00846-021 frequency (hz) magnitude of output impedance ( ? ) 100 0.01 10 1m 10 0.1 100 1 10k 100k 1k without c n * with c n * *see figure 32. figure 20. magnitude of outp ut impedance vs. frequency
ad797 rev. h | page 9 of 20 v out 1k ? 1k? 20p f v in ad797 * +v s ?v s * 4 3 6 7 2 00846-022 *see figure 35. figure 21. inverter connection 00846-023 100 90 10 0% 5v 1s figure 22. inverter large-signal pulse response 00846-024 100 90 10 0% 50mv 100ns figure 23. inverter small-signal pulse response v out 100? 600? v in ad797 ** ?v s +v s r s * *value of source resistance ( see the noise and source impedance considerations section). *see figure 35. ** 4 3 6 7 2 00846-025 * figure 24. follower connection 00846-026 100 90 10 0% 5v 1s figure 25. follower large-signal pulse response 00846-027 100 90 10 0% 50mv 100ns figure 26. follower small-signal pulse response
ad797 rev. h | page 10 of 20 ? 00846-028 100 90 10 0% 50mv 500ns figure 27. 16-bit settling time positive input pulse 00846-029 100 90 10 0% 50mv 500ns figure 28. 16-bit settling time negative input pulse 00846-003 90 ?130 300k ?120 300 100 ?110 ?100 100k 30k 10k 3k 1k frequency (hz) thd (db) 0.001 0.0003 0.0001 thd (%) measurement limit figure 29. thd vs. frequency
ad797 rev. h | page 11 of 20 theory of operation the architecture of the ad797 was developed to overcome inherent limitations in previous amplifier designs. previous precision amplifiers used three stages to ensure high open-loop gain (see figure 30 ) at the expense of additional frequency com- pensation components. slew rate and settling performance are usually compromised, and dynamic performance is not adequate beyond audio frequencies. as can be seen in figure 30 , the first stage gain is rolled off at high frequencies by the compensation network. second stage noise and distortion then appears at the input and degrade performance. the ad797, on the other hand, uses a single ultrahigh gain stage to achieve dc as well as dynamic precision. as shown in the simplified schematic ( figure 31 ), node a, node b, and node c track the input voltage, forcing the operating points of all pairs of devices in the signal path to match. by exploiting the inherent matching of devices fabricated on the same ic chip, high open-loop gain, cmrr, psrr, and low v os are guaranteed by pairwise device matching (that is, npn to npn and pnp to pnp), not by an absolute parameter such as beta and the early voltage. r1 r1 c1 g m g m gain = g m r1 5 10 6 gain = g r1 a2 a3 m c1 r2 buffer buffer r l r l v out v out a. b. a2 a3 c2 00846-030 figure 30. model of ad797 vs. that of a typical three-stage amplifier r2 r1 i5 v out q1 q2 +in ?in r3 q5 c q6 i7 i1 i4 i6 q12 q8 q9 q11 q10 q3 q7 q4 ab c n c c v ss v cc 00846-0 31 figure 31. ad797 simplified schematic this matching benefits not just dc precision, but, because it holds up dynamically, both distortion and settling time are also reduced. this single stage has a voltage gain of >5 10 6 and v os < 80 v, while at the same time providing a thd + noise of less than ?120 db and true 16-bit settling in less than 800 ns. the elimination of second-stage noise effects has the additional benefit of making the low noise of the ad797 (<0.9 nv/hz) extend to beyond 1 mhz. this means new levels of perform- ance for sampled data and imaging systems. all of this performance as well as load drive in excess of 30 ma are made possible by the analog devices, inc., advanced complementary bipolar (cb) process. another unique feature of this circuit is that the addition of a single capacitor, c n (see figure 31 ), enables cancellation of distortion due to the output stage. this can best be explained by referring to a simplified representation of the ad797 using idealized blocks for the different circuit elements ( figure 32 ). a single equation yields the open-loop transfer function of this amplifier; solving it at node b yields ?? = j a c jcj a c g v v c n n m in out where: g m is the transconductance of q1 and q2. a is the gain of the output stage (~1). v out is voltage at the output. v in is differential input voltage. when c n is equal to c c , the ideal single-pole op amp response is attained: cj g v v m in out = in figure 32 , the terms of node a, which include the properties of the output stage, such as output impedance and distortion, cancel by simple subtraction. therefore, the distortion cancellation does not affect the stability or frequency response of the amplifier. with only 500 a of output stage bias, the ad797 delivers a 1 khz sine wave into 60 at 7 v rms with only 1 ppm of distortion. ?in +in q1 q2 i1 i2 v out i3 c a i4 c n c c b 00846-032 current mirror a 1 figure 32. ad797 block diagram
ad797 rev. h | page 12 of 20 2/12 2 ])(4[ s n s n n riktretotale ++= noise and source impedance considerations the ad797 ultralow voltage noise of 0.9 nv/hz is achieved with special input transistors running at nearly 1 ma of collector current. therefore, it is important to consider the total input- referred noise (e n total), which includes contributions from voltage noise (e n ), current noise (i n ), and resistor noise (4 ktr s ). (1) where r s is the total input source resistance. this equation is plotted for the ad797 in figure 33 . because optimum dc performance is obtained with matched source resistances, this case is considered even though it is clear from equation 1 that eliminating the balancing source resistance lowers the total noise by reducing the total r s by a factor of 2. at very low source resistance (r s < 50 ), the voltage noise of the amplifier dominates. as source resistance increases, the johnson noise of r s dominates until a higher resistance of r s > 2 k is achieved; the current noise component is larger than the resistor noise. 00846-033 100 1 10 0.1 10 100 1000 10000 source resistance ( ? ) noise (nv/ hz) total noise resistor noise only figure 33. noise vs. source resistance the ad797 is the optimum choice for low noise performance if the source resistance is kept <1 k. at higher values of source resistance, optimum performance with respect to only noise is obtained with other amplifiers from analog devices ( table 5 ). for up to date information, see an-940 at www.analog.com table 5. recommended amplifiers for different source impedances r s (k) recommended amplifier 0 to <1 ad8597 / ad8599, ad797 , ada4004- 1/ ada4004-2 / ada4004-4 , ad8671/ ad8672/ ad8674 1 to <10 ad8675 / ad8676, ada4075-2 , ada4004-1 / ada4004-2 / ada4004-4 , op1177, op27/ op37, op184 10 to <100 ad8677 , op1177, op2177, op4177, op471 >100 ad8610 / ad8620, ad8605 / ad8606/ ad8608, ada4627-1 , op97, ad548 , ad549, ad745 low frequency noise analog devices specifies low frequency noise as a peak-to-peak quantity in a 0.1 hz to 10 hz bandwidth. several techniques can be used to make this measurement. the usual technique involves amplifying, filtering, and measuring the amplifier noise for a predetermined test time. the noise bandwidth of the filter is corrected for, and the test time is carefully controlled because the measurement time acts as an additional low frequency roll-off. the plot in figure 6 uses a slightly different technique: an fft- based instrument ( figure 34 ) is used to generate a 10 hz brickwall filter. a low frequency pole at 0.1 hz is generated with an external ac coupling capacitor, which is also the instrument being dc coupled. several precautions are necessary to attain optimum low frequency noise performance: ? care must be used to account for the effects of r s . even a 10 resistor has 0.4 nv/hz of noise (an error of 9% when root sum squared with 0.9 nv/hz). ? the test setup must be fully warmed up to prevent e os drift from erroneously contributing to input noise. ? circuitry must be shielded from air currents. heat flow out of the package through its leads creates the opportunity for a thermoelectric potential at every junction of different metals. selective heating and cooling of these by random air currents appears as 1/f noise and obscures the true device noise. ? the results must be interpreted using valid statistical techniques. 7 4 6 2 3 hp 3465 dynamic signal analyzer (10hz) 1 ? 100k ? * * v out +v s ?v s 1.5f ad797 00846-034 *use the power supply bypassing shown in figure 35. figure 34. test setup for measuring 0.1 hz to 10 hz noise wideband noise due to its single-stage design, the noise of the ad797 is flat over frequencies from less than 10 hz to beyond 1 mhz. this is not true of most dc precision amplifiers, where second-stage noise contributes to input-referred noise beyond the audio frequency range. the ad797 offers new levels of performance in wideband imaging applications. in sampled data systems, where aliasing of out-of-band noise into the signal band is a problem, the ad797 outperforms all previously available ic op amps.
ad797 rev. h | page 13 of 20 bypassing considerations taking full advantage of the very wide bandwidth and dynamic range capabilities of the ad797 requires some precautions. first, multiple bypassing is recommended in any precision application. a 1.0 f to 4.7 f tantalum in parallel with 0.1 f ceramic bypass capacitors are sufficient in most applications. when driving heavy loads, a larger demand is placed on the supply bypassing. in this case, selective use of larger values of tantalum capacitors and damping of their lead inductance with small-value (1.1 to 4.7 ) carbon resistors can achieve an improvement. figure 35 summarizes power supply bypassing recommendations. use short lead lengths (<5mm) load current kelvin return or 0 .1 f v s v s 4.7f 00846-035 use short lead lengths (<5mm) load current kelvin return 0.1f 4.7f to 22.0f 1.1 ? to 4.7 ? figure 35. recommended power supply bypassing the noninverting configuration ultralow noise requires very low values of the internal parasitic resistance (r bb ) for the input transistors (6 ). this implies very little damping of input and output reactive interactions. with the ad797, additional input series damping is required for stability with direct output to input feedback. a 100 resistor (r1) in the inverting input ( figure 36 ) is sufficient; the 100 balancing resistor (r2) is recommended but is not required for stability. the noise penalty is minimal (e n total 2.1 nv/hz), which is usually insignificant. 7 4 3 r2 100? r1 100 ? * v o u t v i n +v s * ?v s ad797 00846-036 r l 600 ? 6 2 * use the power supply bypassing shown in figure 35. figure 36. voltage follower connection best response flatness is obtained with the addition of a small capacitor (c l < 33 pf) in parallel with the 100 resistor ( figure 37 ). the input source resistance and capacitance also affect the response slightly, and experimentation may be necessary for best results. 7 * *use the power supply bypassing shown in figure 35. * v o u t v i n +v s ?v s ad797 00846-037 c l 6 2 r s c s 3 4 600 ? 100? figure 37. alternative voltage follower connection low noise preamplification is usually performed in the non- inverting mode ( figure 38 ). for lowest noise, the equivalent resistance of the feedback network should be as low as possible. the 30 ma minimum drive current of the ad797 makes it easier to achieve this. the feedback resistors can be made as low as possible, with consideration to load drive and power consumption. 7 * * v o u t v i n +v s ?v s ad797 00846-038 r l c l r2 r1 6 2 3 4 *use the power supply bypassing shown in figure 35. figure 38. low noise preamplifier table 6 provides some representative values for the ad797 when used as a low noise follower. operation on 5 v supplies allows the use of a 100 or less feedback network (r1 + r2). because the ad797 shows no unusual behavior when operating near its maximum rated current, it is suitable for driving the ad600/ ad602 (see figure 50 ) while preserving low noise performance. optimum flatness and stability at noise gains >1 sometimes require a small capacitor (c l ) connected across the feedback resistor (r1 of figure 38 ). table 6 includes recommended values of c l for several gains. in general, when r2 is greater than 100 and c l is greater than 33 pf, a 100 resistor should be placed in series with c l . source resistance matching is assumed, and the ad797 should not be operated with unbalanced source resistance >200 k/g. table 6. values for follower with gain circuit gain r1 r2 c l noise (excluding r s ) 2 1 k 1 k 20 pf 3.0 nv/hz 2 300 300 10 pf 1.8 nv/hz 10 33.2 300 5 pf 1.2 nv/hz 20 16.5 316 1.0 nv/hz >35 10 (g ? 1) 10 0.98 nv/hz
ad797 rev. h | page 14 of 20 the i-to-v converter is a special case of the follower configu- ration. when the ad797 is used in an i-to-v converter, for example as a dac buffer, the circuit shown in figure 39 should be used. the value of c l depends on the dac, and if c l is greater than 33 pf, a 100 series resistor is required. a bypassed balancing resistor (r s and c s ) can be included to minimize dc errors. 7 * * v o u t +v s ad797 ?v s 00846-039 r 1 r i in c s s 6 3 4 100 ? 600? 20p f to 120pf 2 * use the power supply bypassing shown in figure 35. figure 39. i-to-v converter connection the inverting configuration the inverting configuration (see figure 40 ) presents a low input impedance, r1, to the source. for this reason, the goals of both low noise and input buffering are at odds with one another. nonetheless, the excellent dynamics of the ad797 makes it the preferred choice in many inverting applications, and with careful selection of feedback resistors, the noise penalties are minimal. some examples are presented in table 7 and figure 40 . 7 * * v o u t v i n +v s ad797 ?v s 00846-040 r 2 r l r1 c l r s 6 3 4 2 *use the power supply bypassing shown in figure 35. figure 40. inverting amplifier connection table 7. values for inverting circuit gain r1 r2 c l noise (excluding r s ) ?1 1 k 1 k 20 pf 3.0 nv/hz ?1 300 300 10 pf 1.8 nv/hz ?10 150 1500 5 pf 1.8 nv/hz driving capacitive loads the capacitive load driving capabilities of the ad797 are displayed in figure 41 . at gains greater than 10, usually no special precautions are necessary. if more drive is desirable, however, the circuit shown in figure 42 should be used. for example, this circuit allows a 5000 pf load to be driven cleanly at a noise gain 2. 00846-041 100n f 10nf 1pf 100 10 11 1nf 100pf 10pf closed-loop gain c k a pacitive load drive c a pability figure 41. capacitive load drive capability vs. closed-loop gain 7 * * v o u t v i n +v s ?v s ad797 00846-042 c1 20p f 200pf 6 3 4 2 33 ? 100? 1k? 1k ? *use the power supply bypassing shown in figure 35. figure 42. recommended circuit for driving a high capacitance load settling time the ad797 is unique among ultralow noise amplifiers in that it settles to 16 bits (<150 v) in less than 800 ns. measuring this performance presents a challenge. a special test circuit (see figure 43 ) was developed for this purpose. the input signal was obtained from a resonant reed switch pulse generator, available from tektronix as calibration fixture no. 067-0608-00. when open, the switch is simply 50 to ground and settling is purely a passive pulse decay and inherently flat. the low repetition rate signal was captured on a digital oscilloscope after being amplified and clamped twice. the selection of plug-in for the oscilloscope was made for minimum overload recovery.
ad797 rev. h | page 15 of 20 v er r o r 5 ?v s +v s +v s v in ?v s 00846-043 to tektronix 7a26 oscilloscope preamp input section (via less than 1ft 50? coaxial cable) tektronix calibration fixture 2 hp2835 2 hp2835 1m ? 226 ? 51pf 1k? 1k? 1k ? 1k? 100? 250? 0.47f 1f 0.1f 0.47f 4.26k ? 20pf 20pf notes use circuit board with ground plane. 1f 0.1f 7 3 6 2 a2 ad829 a1 ad797 4 7 3 6 2 4 + ? + ? figure 43. settling time test circuit distortion reduction the ad797 has distortion performance (thd < ?120 db, @ 20 khz, 3 v rms, r l = 600 ) unequaled by most voltage feedback amplifiers. at higher gains and higher frequencies, thd increases due to a reduction in loop gain. however, in contrast to most conven- tional voltage feedback amplifiers, the ad797 provides two effective means of reducing distortion as gain and frequency are increased: cancellation of the distortion of the output stage and gain bandwidth enhancement by decompensation. by applying these techniques, gain bandwidth can be increased to 450 mhz at g = 1000, and distortion can be held to ?100 db at 20 khz for g = 100. the unique design of the ad797 provides cancellation of the output stages distortion. to achieve this, a capacitance equal to the effective compensation capacitance, usually 50 pf, is connected between pin 8 and the output (see c2 in figure 44 ). use of this feature improves distortion performance when the closed-loop gain is more than 10 or when frequencies of interest are greater than 30 khz. bandwidth enhancement via decompensation is achieved by connecting a capacitor from pin 8 to ground (see c1 in figure 44 ). adding c1 results in subtracting from the value of the internal compensation capacitance (50 pf), yielding a smaller effective compensation capacitance and therefore a larger bandwidth. the benefits of adding c1 are evident for closed-loop gains of 100. a maximum value of 33 pf at gains of 1000 is recommended. at a gain of 1000, the bandwidth is 450 khz. table 8 and figure 45 summarize the performance of the ad797 with distortion cancellation and decompensation. v i n a. b . ad797 00846-044 50pf r1 r2 r2 c1, see table c2 = 50pf ? c1 6 2 3 v i n ad797 c2 c1 r1 6 2 3 8 8 v o u t figure 44. recommended connections for distortion cancellation and bandwidth enhancement table 8. recommended external compensation for distortion cancellation and bandwidth enhancement a/b a b gain r1 () r2 () c1 (pf) c2 (pf) 3 db bw c1 (pf) c2 (pf) 3 db bw 10 909 100 0 50 6 mhz 0 50 6 mhz 100 1 k 10 0 50 1 mhz 15 33 1.5 mhz 1000 10 k 10 0 50 110 khz 33 15 450 khz 00846-045 ?80 300k ?120 300 100 ?110 ?100 ?90 100k 30k 10k 3k 1k frequency (hz) thd (db) 0.01 0.003 0.001 0.0003 0.0001 thd (%) noise limit, g = +1000 noise limit, g = +100 g = +1000 r l = 600 ? g = +1000 r l = 10k ? g = +10 r l = 600 ? g = +100 r l = 600 ? figure 45. total harmonic distortion (thd) vs. frequency @ 3 v rms for figure 44 b
ad797 rev. h | page 16 of 20 differential line receiver the differential receiver circuit of figure 46 is useful for many applications, from audio to mri imaging. the circuit allows extraction of a low level signal in the presence of common- mode noise. as shown in figure 47 , the ad797 provides this function with only 9 nv/hz noise at the output. figure 48 shows the ad797 20-bit thd performance over the audio band and the 16-bit accuracy to 250 khz. ** ** ad797 00846-046 6 2 3 1k ? differential input 1k ? 1k? 1k? 20pf 50pf* 20p f ?v s +v s 4 7 8 v o u t optional use the power supply bypassing shown in figure 35. * ** figure 46. differential line receiver 00846-047 6 10m 100 10 1m 100k 10k 1k 16 12 8 10 14 frequency (hz) output voltage noise (nv/ hz) figure 47. output voltage noise spectral density for differential line receiver 00846-048 frequency (hz) thd (db) thd (%) ? 90 300k ?120 ?130 300 100 ?110 ?100 100k 30k 10k 3k 1k 0.003 0.0003 0.001 0.0001 without optional 50pf c n with optional 50pf c n measurement limit figure 48. total harmonic distortion (thd) vs. frequency for differential line receiver a general-purpose ate/instrumentation i/o driver the ultralow noise and distortion of the ad797 can be combined with the wide bandwidth, slew rate, and load drive of a current feedback amplifier to yield a very wide dynamic range general-purpose driver. the circuit shown in figure 49 combines the ad797 with the ad811 in just such an application. using the component values shown, this circuit is capable of better than ?90 db thd with a 5 v, 500 khz output signal. the circuit is, therefore, suitable for driving a high resolution adc as an output driver in automatic test equipment (ate) systems. using a 100 khz sine wave, the circuit drives a 600 load to a level of 7 v rms with less than ?109 db thd and a 10 k load at less than ?117 db thd. * 7 * * * +v s +v s ?v s ad797 00846-049 22p f 2k ? 649 ? 649? 1k? r2 6 3 4 2 7 ad811 6 2 4 3 ?v s *use the power supply bypassing shown in figure 35. v out v in figure 49. a general-purpose ate/instrumentation i/o driver
ad797 rev. h | page 17 of 20 00846-052 100m 1k 100 100 0 60 20 40 80 10m 1m 100k 10k frequency (hz) voltage noise (mv rms (0.1hz frequency)) v out (db re 1v/a) ?80 ? 30 ?50 ?70 ?60 ?40 noise v out ultrasound/sonar imaging preamp the ad600 variable gain amplifier provides the time-controlled gain (tcg) function necessary for very wide dynamic range sonar and low frequency ultrasound applications. under some circumstances, it is necessary to buffer the input of the ad600 to preserve its low noise performance. to optimize dynamic range, this buffer should have a maximum of 6 db of gain. the combination of low noise and low gain is difficult to achieve. the input buffer circuit shown in figure 50 provides 1 nv/hz noise performance at a gain of 2 (dc to 1 mhz) by using 26.1 resistors in its feedback path. distortion is only ?50 dbc at 1 mhz for a 2 v p-p output level and drops rapidly to better than ?70 dbc at an output level of 200 mv p-p. * 7 * * * +v s v out ad797 v s = 6vdc 00846-050 26.1 ? 26.1 ? 6 3 4 2 figure 52. total integrated voltage noise and v out of amorphous detector preamp professional audio signal processingdac buffers ?v s ad600 v in the low noise and low distortion of the ad797 make it an ideal choice for professional audio signal processing. an ideal i-to-v converter for a current output dac would simply be a resistor to ground, were it not for the fact that most dacs do not operate linearly with voltage on their output. standard practice is to operate an op amp as an i-to-v converter, creating a virtual ground at its inverting input. normally, clock energy and current steps must be absorbed by the op amp output stage. however, in the configuration shown in figure 53 , capacitor c f shunts high frequency energy to ground while correctly reproducing the desired output with extremely low thd and imd. *use the power supply bypassing shown in figure 35. figure 50. an ultrasound preamplifier circuit amorphous (photodiode) detector large area photodiodes (c s 500 pf) and certain image detectors (amorphous si) have optimum performance when used in conjunction with amplifiers with very low voltage (rather than very low current noise). figure 51 shows the ad797 used with an amorphous si (c s = 1000 pf) detector. the response is adjusted for flatness using capacitor c l , and the noise is dominated by voltage noise amplified by the ac noise gain. the ad797s excellent input noise performance gives 27 v rms total noise in a 1 mhz bandwidth, as shown by figure 52 . 7 * * +v s ?v s ad797 00846-053 c f 82pf 6 2 c1 2000pf 4 100? 3k ? ad1862 dac 3 v out *use the power supply bypassing shown in figure 35. * 7 * 00846-051 +v s i s ad797 10k ? 100 ? c l 50pf c s 1000pf 6 3 4 2 ?v s v out figure 53. a professional audio dac buffer v out 7 + v s ?v s ad797 6 2 4 3 1 5 v os adjust 00846-054 ?in +in 20k? *use the power supply bypassing shown in figure 35. figure 51. amorphous detector preamp figure 54. offset null configuration
ad797 rev. h | page 18 of 20 compliant to jedec standards ms-001 controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design. corner leads may be configured as whole or half leads. 070606-a 0.022 (0.56) 0.018 (0.46) 0.014 (0.36) outline dimensions seating plane 0.015 (0.38) min 0.210 (5.33) max 0.150 (3.81) 0.130 (3.30) 0.115 (2.92) 0.070 (1.78) 0.060 (1.52) 0.045 (1.14) 8 1 4 5 0.280 (7.11) 0.250 (6.35) 0.240 (6.10) 0.100 (2.54) bsc 0.400 (10.16) 0.365 (9.27) 0.355 (9.02) 0.325 (8.26) 0.310 (7.87) 0.300 (7.62) 0.060 (1.52) max 0.430 (10.92) max 0.014 (0.36) 0.010 (0.25) 0.008 (0.20) 0.195 (4.95) 0.130 (3.30) 0.115 (2.92) 0.015 (0.38) gauge plane 0.005 (0.13) min figure 55. 8-lead plastic dual in-line package [pdip] narrow body (n-8) dimensions shown in inches and (millimeters) controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design. compliant to jedec standards ms-012-aa 012407-a 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) 0.50 (0.0196) 0.25 (0.0099) 45 8 0 1.75 (0.0688) 1.35 (0.0532) seating plane 0.25 (0.0098) 0.10 (0.0040) 4 1 85 5.00 (0.1968) 4.80 (0.1890) 4.00 (0.1574) 3.80 (0.1497) 1.27 (0.0500) bsc 6.20 (0.2441) 5.80 (0.2284) 0.51 (0.0201) 0.31 (0.0122) coplanarity 0.10 figure 56. 8-lead standard small outline package [soic_n] narrow body (r-8) dimensions shown in millimeters and (inches)
ad797 rev. h | page 19 of 20 ordering guide model 1 temperature range package description package option ad797anz ?40c to +85c 8-lead plastic dual in-line package [pdip] n-8 ad797ar ?40c to +85c 8-lead standard small outline package [soic_n] r-8 ad797ar-reel ?40c to +85c 8-lead standard small outline package [soic_n] r-8 ad797ar-reel7 ?40c to +85c 8-lead standard small outline package [soic_n] r-8 ad797arz ?40c to +85c 8-lead standard small outline package [soic_n] r-8 ad797arz-reel ?40c to +85c 8-lead stan dard small outline package [soic_n] r-8 ad797arz-reel7 ?40c to +85c 8-lead standa rd small outline package [soic_n] r-8 ad797br ?40c to +85c 8-lead standard small outline package [soic_n] r-8 ad797br-reel ?40c to +85c 8-lead standard small outline package [soic_n] r-8 ad797br-reel7 ?40c to +85c 8-lead standard small outline package [soic_n] r-8 ad797brz ?40c to +85c 8-lead standard small outline package [soic_n] r-8 AD797BRZ-REEL ?40c to +85c 8-lead standard small outline package [soic_n] r-8 AD797BRZ-REEL7 ?40c to +85c 8-lead standard small outline package [soic_n] r-8 1 z = rohs compliant part.
ad797 rev. h | page 20 of 20 notes ?2002-2010 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d00846-0-6/10(h)

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